List of Posters

Venkateshwar Kottapalli and Flemming Andersen.
Formal Property Verification of a MESI-based Cache Implementation
Abstract: The design and verification of cache coherency is complex due to non-atomic transitions in hardware implementation. Simulation-based techniques fail to ensure the absence of design failures. Formal methods can identify the numerous race conditions and corner cases. In this study, we perform formal property verification (FPV) of a 4-core snooping cache design with private L1 cache, shared L2 cache, and an atomic bus. We present the advantages of FPV over a state of the art UVM verification environment.
Ignatius Praveen Lawrence and Duncan Walker.
Optimal Test Conditions and Scenario for Detecting Resistive Opens in Latches and Flip-Flops

Abstract: Stuck-At and Transition Delay Fault models have been used to screen defective chips. These fault models are not sufficient to detect resistive opens. Our work proposes aggressive test conditions and scenario for detecting subtle resistive opens. The aim is to improve quality of chips especially in safety critical applications.
Hui Jiang and Jennifer Dworak.
Enhancing Cell-Aware Fault Detection through Intelligent Use of Scan Shift Cycles

Abstract: In this paper, we investigate the ability of the intervening shift cycles to achieve high static cell-aware fault coverage using only the test patterns generated to detect stuck-at faults. We also investigate reducing the number of shadow flops required. Our results show that high cell-aware coverage is achievable even when only a stuck-at test set is applied—in some cases equal to the coverage obtained by a dedicated cell-aware test set.
Jiafan Wang and Jiang Hu.
Thwarting Analog IC Piracy via Combinational Locking

Abstract: A combinational locking technique is introduced to enhance analog IC security against piracy. The kernel idea is reconfigurable current mirror design using Satisfiability Modulo Theories. With the locking system, only a single key value can make analog IC operate properly. The effectiveness is confirmed by simulations on analog IC designs.
Shilpi Sharma and Rashaunda Henderson.
Predictive Method for Multiplexing Laguerre-Gaussian Beams at Radio Frequencies

Abstract: This research focuses on developing predictive techniques to combine with experimental demonstrations of orbital angular momentum multiplexing. Laguerre Gaussian beams contain an orbital angular momentum phase term, which can be exploited to increase the data rate of communication systems. Using MATLAB toolkits we are trying to build a numerical framework for multiplexing and demultiplexing message signals in E-band (73 GHz) that we have carried out using impulse radios.
Abbas Fairouz and Sunil Khatri.
A Comparison of Low Standby Power Techniques for an Asynchronous NoC Router

Abstract: The Network-on-Chip (NoC) paradigm is now widely used to interconnect the processing elements (PEs) in a chip multiprocessor (CMP). It has been reported that the NoC consumes about a third of the total power consumption of the multi-core processor. To address this, asynchronous NoC routers have been proposed, to eliminate the clocking power associated with the NoC implementation. In this work, we present a comparison of techniques to reduce the standby power of a state-of-the-art asynchronous NoC router.
Wenbin Xu and Jiang Hu.
A Simple Yet Efficient Accuracy Configurable Adder Design

Abstract: Approximate computing is a promising approach to low power IC design and recently received considerable attention. In this work, we investigate a simple accuracy configurable adder design that contains small redundancy and uses very simple carry prediction. Simulation results show that our design dominates previous work on accuracy-delay-power tradeoff while uses 39% less area.
Mallika Pokharel and Duncan M. (Hank) Walker.
Multi-cycle At Speed Test

Abstract: We use multiple functional cycles for compacting K-longest paths per gate to generate minimal patterns. Each path delay test is compared to at-speed patterns in the pool. We try to place each path in the first pattern in first capture cycle. If it fails, we exploit other capture cycles.
Abbas Fairouz and Sunil Khatri.
Design of a Hardware Hash Unit for use in Modern Microprocessors

Abstract: In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used. Hashing is a key algorithm that is extensively used in such applications. Thus, implementing a hardware-based hash unit as a new special function unit on a modern microprocessor would potentially increase performance significantly. In this work, we present the microarchitecture and circuit designs for a hardware hash unit (HU) for modern microprocessors.
Zachary Simpson and Gayatri Metha.
Solving Complex and Constrained Mapping Problems using Interactive Design Framework

Abstract: Untangled III is an online interactive mapping/placement game to harness human intelligence for large, complex, and constrained mapping problems. This game is broadly accessible and it does not require any engineering background to play. Players can easily build upon other players’ solutions using the community play feature of the game.
Yi Sun and Jennifer Dworak.
Using FPGA as a Tester in a 3D stacked IC

Abstract: Using FPGA as a tester in a 3D stacked IC provides options for different testers for different company, using an FPGA as a tester reduces the power consumption when compared to Embedded Deterministic Test.
Gity Karami and Jeff Tian.
Improving Web Application Reliability and Testing Using Accurate Usage Models

Abstract: Markov OP is a good candidate for effective web quality and reliability assurance because it captures the behavior of web components and related navigation facilities to support usage based statistical testing (UBST). The accuracy of such usage models would affect the effectiveness of quality assurance and testing activities. We examine the impact of accurate usage models on reliability, test coverage, and test efficiency.
Soha Alhelay and Jennifer Dworak.
Detecting a Trojan Die in 3-D Stacked Integrated Circuits

Abstract: 3D integrated circuits introduce both advantages and disadvantages for security. Among the disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between two legitimate dies. We propose a Trojan detection technique and the required architecture to measure the propagation delays across the 3D dies to detect and locate the extra die in a 3D die stack.
Nirosha Dinayadura and Armin Mikler.
An Efficient Approach for Outbreak Preparedness for Dengue

Abstract: Dengue is the world's fastest growing vector-borne disease. An efficient integrated solution that addresses broad aspects of the dengue mitigation is presented. Support Vector Regression ensemble; dengue epidemic prediction; and a development of a surveillance system to effectively monitor case data were cooperatively implemented in the proposed system.